A Novel Power Optimized Sparse Kogge Approach for Implementing FM0 and Manchester Encoding Techniques

Authors:CHOLLANGI VISHALA, G. VASU, M. J. M. PRASAD, B. KALAYAN KUMAR, DR. D. RANGARAJU

0001-0007

A 64-Bit Kogge Stone Cary Save Adder is Designed for Reducing Area by using Zero Finding Logic

Authors:B. CHARAN KUMAR, A. UDAY KUMAR

0008-0011

Implementation of Spanning Tree Based Add-Multiply Operator for Optimized Power Applications

Authors:KARRI JANAKI JYOTHIRMAI, K. SANGEET KUMAR

0012-0017

Implementation of IEEE 754 Standard Floating Point Arithmetic Operations via Exponent Adder

Authors:D. RAM SANDEEP, K. GOVINDARAO

0018-0021

High Performance and Area Efficient Booth Wallace Multiplier

Authors:POTNURU VENKATA SATYA SAI RAJU, KOMMU PRAKASH RAO

0022--0025

An Implementation of Detecting and Correcting Multiple Bit Upsets in Static Random Access Memories

Authors:A. RUPAVATHI, K. YOGITHA BALI

0026-0031

Low Power Approach For Implementation of Encoder and Decoder with 3-Bit Ripple Counter Used for High Speedcommunication

Authors:J. NEERAJA, K. MANJUNATH

0032-0036

Realization of Power and Area Optimized Aging-Aware Multiplier

Authors:BANDA BHARADWAJ, P. VISWESWARARAO

0037-0042

Power Optimized Evaluation of Reliable Truncated Multiplier

Authors:K V V VENKATA RAMANA, NALINI GUTTULA

0043-0046

Realization of Power Optimized Error Correcting Codes using Hamming Technique

Authors:SATEESH MUTYALA, NALINI GUTTULA

0047-0051